1. Field of the Invention
The present invention relates to a memory circuit that is constituted of a memory holding circuit including a memory holding part formed on a semiconductor substrate. More particularly, it is effectively used as a memory circuit with a memory holding circuit such as a register file, SRAM (static random access memory), etc.
2. Description of the Related Art
Conventionally, a memory circuit with a large number of ports requires a large number of internal signal lines such as word lines, bit lines, etc., which are disposed adjacent to each other for saving the area. Therefore, in accordance with micronization of the process, crosstalk glitches between each of the signals have become conspicuous. As a measure for this, there has been proposed a crosstalk-glitch suppressor circuit (referred to as a suppressor circuit hereinafter) (see Japanese Patent Unexamined Publication 2001-14858, Japanese Granted Patent Publication No. 3057990, for example).
Although providing an effect, the suppressor circuit is also a load to the internal signal lines, which causes an increase in the power consumption and deterioration in the operation speed. For example, referring to the case of the suppressor circuit disclosed in Japanese Patent Unexamined Publication 2001-14858, as shown in FIG. 4, writing word line WWL1-1 is fixed to non-selected potential for suppressing crosstalk glitches when a reading-out word line RWL1-2 is a selected potential. On the other hand, drain capacitance is additionally applied to the writing word line and gate capacitance is additionally applied to the reading-out word line as well, thereby causing an increase in the power and deterioration in the operation speed for the amounts of those capacitances.
There are cases without having a problem of crosstalk glitches depending on conditions of power supply voltage, process state, operation frequency, etc. Under such conditions, there is no suppressor circuit required and, inversely, a bad influence may be exerted on the power due to a heavy load to the wirings and on the operation speed especially when the operating power supply voltage is low.